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■ Abbreviation / Long Form : GAA / gate-all-around

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Total Number of Papers: 21
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Abbreviation:   GAA  (>> Co-occurring Abbreviation)
Long Form:   gate-all-around
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No. Year Title Co-occurring Abbreviation
2019 Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits. AC, ARs, CMOS, DC, MOSFET, NW, WKF
2019 Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor. SS, TCAD, TFET
2019 Effect of Interface Traps on the Device Performance of InGaAs-Based Gate-All-Around Tunneling Field-Effect Transistors. SS, TCAD, TFETs
2019 Nanoscale FET-Based Transduction toward Sensitive Extended-Gate Biosensors. FET
2019 Variability-Aware Simulation Strategy for Gate-All-Around Vertical Field Effect Transistor. GV, TCAD, VFET, WFV
2018 Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET). A-TFET, Lg, TCAD
2018 The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory. ---
2017 Highly gate-tuneable Rashba spin-orbit interaction in a gate-all-around InAs nanowire metal-oxide-semiconductor field-effect transistor. FET, MOSFETs
2016 A Vertically Integrated Junctionless Nanowire Transistor. IM-FET, JL-FET, SiNWs, VJ-FET, VM-FET
10  2016 Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor. ---
11  2016 Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around. DIBL, SCE, SS, VNW
12  2016 Vertically Integrated Nanowire-Based Unified Memory. DRAM, ORADEP, SoC, UM, VIUM
13  2015 Origin of anomalous piezoresistive effects in VLS grown Si nanowires. FET, NWs, TSD, VLS
14  2014 A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory. JL-FinFET, NVM, OTP
15  2014 Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor. JL, TFTs
16  2013 A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope. FETs, NWs
17  2013 Analysis on RF parameters of nanoscale tunneling field-effect transistor based on InAs/InGaAs/InP heterojunctions. BTBT, Cg, DC, lon, LSTP, max, Si, TFETs
18  2012 Electrical properties of 10-nm-radius n-type gate all around twin Si nanowire field effect transistors. FETs, TSNWFETs
19  2012 Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique. NW
20  2011 An explicit continuous analytical model for Gate All Around (GAA) MOSFETs including the hot-carrier degradation effects. GS
21  2009 Phonon- and surface-roughness-limited mobility of gate-all-around 3C-SiC and Si nanowire FETs. FETs, NEGF, NW